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Intel Physical Design Implementation Engineer in Fort Collins, Colorado

Job Description

Join Intel-and engineer the future!

Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help create the next generation of technologies that will shape the future for decades to come.

Intel’s IP Engineering Group invites you to be part of a senior team dedicated to developing and leading backend design methodology for ground-breaking high-performance IPs. This is a unique chance to join an experienced team, as we continue transforming ourselves into the IP supplier of choice for flagship Intel SoCs. Current efforts include design innovations to achieve best in class performance across a broad scope of IPs and process technologies, as well as defining and driving methodology advancement across the IP execution teams.

As a Physical Design Implementation Engineer, this position focuses on design implementation methodology on internal and external process nodes for top level construction using tools and solutions from multiple vendors including Synopsys and Cadence.

You must have hands-on and in-depth knowledge of SoC Physical design flow from high level design to synthesis, place and route, timing and power, to creating a design database that is ready for manufacturing. You should also have the technical expertise, knowledge, and experience to:

  • Mentor and develop engineers in specific physical design domains

  • Effectively communicate with larger numbers of design engineers, providing high quality documentation and presentations

  • Guide and collaborate with partner domains like Logic, Design Automation, test, etc., to optimize for convergence

  • Coordinate with other methodology disciplines to ensure a seamless design execution approach

  • Work in a cross-site/cross-division work model and influence the broader group by participating or facilitating work groups.

Responsibilities will be tailored to the candidate's skills and expertise and will include the following, but not be limited to:

  • Develop methodology of Design Planning/floor planning of complex blocks and plan efficient partitioning and budgeting techniques

  • Plan globals such as power grid design, pin placements, clock drop off points, DFM features, ESD requirements for complex IPs and drive other design teams to use the best-known methods

  • Own top Level planning including bump placements, top metals, MIM caps etc.

  • Explore and innovate into new automation technologies in place and route, as well as expansion and enablement of internal and external leading process technology nodes.

  • Continuously evaluate tools and features to improve design cycle time and QOR. Assist in streamlining execution process through problem solving and developing utilities to improve automation and debug.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements

Candidate must have a Bachelor's degree in Electrical/Computer Engineering or other related field of study and 6+ years of experience in:

  • SOC/IP physical design

  • Physical design convergence and tape-in

  • Interconnect design and analysis

  • Translation of architectural specification into physical domain

  • Layout design

Preferred Qualifications

5+ years of experience with:

  • Multiple automation vendors, especially Cadence design construction tools

  • External process nodes

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.