Intel Logic Designer in Fort Collins, Colorado
Join our world-class IP development team. In this role you are a logic design engineer and member of an IP team chartered with delivering memory IP and memory controller subsystems to multiple Intel server SoCs. This IP team develops a wide range of memory technologies and delivers to SoCs across the Intel portfolio.
Responsibilities will include but not be limited to:
Oversee definition, design, verification, and documentation of IP within SoC (System on a Chip) development
Understand coding principles as applied to high speed digital design
Create specifications to describe logic function
Code Verilog designs to match the specification
Evaluate timing reports and apply learning to meet timing requirements
Communicate design details to verification team
Train end users on design functionality
Debug issues to root cause, including supporting pre- and post-silicon validation teams
Key skills and experience may include:
IP or SoC development using Verilog/SystemVerilog in Open Verification Methodology (OVM)/Universal Verification Methodology (UVM)
Writing System Verilog Assertions (SVA)
Interpreting code coverage results to augment better design verification outcomes
Collaborating with verification partners within verification environments that include use of constrained-random stimulus and functional coverage
Colorado Pay Transparency Law requires that Intel discloses the compensation for jobs which could be performed in Colorado. Intel anticipates that the annual base pay range for this role in Colorado is min $130,020.00 - max $195,420.00.
In addition to base pay, regular Intel employees are eligible for an Annual Performance Bonus (“APB”) and Quarterly Profit Bonus (“QPB”). Payout of APB is subject to eligibility and other program conditions as well as the Company’s performance to its operational and financial goals. Payout of QPB connects Intel’s employees to the quarterly profits of the Company. Employees in eligible sales and marketing positions receive commission in lieu of APB but are eligible for QPB. Information about these bonus programs as well as the host of expansive stock, health, retirement and vacation benefits offered to Intel employees are available at https://www.intel.com/content/www/us/en/jobs/benefits.html Interns and Intel Contract Employees are not eligible for APB or QPB or for some employee benefits including, but not limited to, disability, life insurance, retirement, equity and certain leave programs.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have a Bachelors of Science in Electrical/Computer Engineering or related field of study and 6+ years of experience or a Masters in Electrical/Computer Engineering or related field of study and 4+ years of experience or a PhD in Electrical/Computer Engineering or related field of study and 2+ years of experience in:
Logic Design in System Verilog
Experience using Industry Standard EDA tools
- Experience in development of memory controllers using memory protocols for DDR and HBM
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
US, California, Santa Clara
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.