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Seakr Engineering, Inc. Engineer III, Verification Engineering in Centennial, Colorado

Company DescriptionSEAKR is seeking a Verification Engineer who is responsible for developingverification and simulation strategies, conducting design reviews,creating a digital test plan and providing coverage metrics.The Engineer is responsible for the construction and maintenance of simulationenvironments using System Verilog with UVM (Universal VerificationMethodology), and performing and evaluating regression tests for a designunder test.The candidate must be able to extract and derive test requirements andsequences for an interface or interfaces based on available designdocumentation and requirements.Ability to architect and construct full test environments for simple devicesusing UVM, including coverage, is required.The candidate shall be capable of diagnosing sophisticated test failures andfiling results and be capable of analyzing code coverage to adjust agentsequence behavior.Ability to analyze Verilog RTL to diagnose test failures is required.Ability to diagnose VHDL RTL is a plus.Ability to perform and evaluate regression tests for a design under test is aplus.Ability to use simulation tools such as Mentor Graphics Modelsim/Questasimfor simulation debug and reporting is required.Must be able to work effectively under pressure to meet tight deadlines.Experience verifying DSP related designs is a plus.Job DescriptionA Bachelors degree in Electrical Engineering or Computer Science and at least7 years of verification engineering experience are required. A Master'sDegree is preferred.Additional InformationAll your information will be kept confidential according to EEO guidelines

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